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DA9081.006 1 August, 2005
MAS9081
* Dual Band Receiver IC * High Sensitivity * Very Low Power Consumption * Wide Supply Voltage Range * Power Down Control * Control for AGC On * High Selectivity by Crystal Filter * Fast Startup Feature
DESCRIPTION
The MAS9081 AM-Receiver chip is a highly sensitive, simple to use AM receiver specially intended to receive time signals in the frequency range from 40 kHz to 100 kHz. Only a few external components are required for time signal receiving. The circuit has preamplifier, wide range automatic gain control, demodulator and output comparator built in. The output signal can be processed directly by an additional digital circuitry to extract the data from the received signal. The control for AGC (automatic gain control) can be used to switch AGC on or off if necessary. MAS9081 supports dual band operation by switching between two crystal filters and an additional antenna tuning capacitor. MAS9081 has differential input and different internal compensation capacitor options for compensating shunt capacitances of different crystals (See ordering information on page 12).
FEATURES
* * * * * * * * * * Dual Band Receiver IC Highly Sensitive AM Receiver, 0.4 VRMS typ. Wide Supply Voltage Range from 1.1 V to 5 V Very Low Power Consumption Power Down Control Fast Startup Only a Few External Components Necessary Control for AGC On Wide Frequency Range from 40 kHz to 100 kHz High Selectivity by Quartz Crystal Filter
APPLICATIONS
* Dual Band Time Signal Receiver WWVB (USA), JJY (Japan), DCF77 (Germany), MSF (UK), HGB (Switzerland) and BPC (China)
BLOCK DIAGRAM
QO2 RFIP RFIM AGC Amplifier Demodulator & Comparator OUT QO1 QI AON
RFI2
Power Supply/Biasing VDD VSS PDN1 PDN2 AGC DEC
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DA9081.006 1 August, 2005
MAS9081 PAD LAYOUT
9081Ax, x=1, 3, 4 or 5
VDD QO2 QO1 QI AGC PDN2 OUT VSS RFI2 RFIM RFIP PDN1 AON DEC
1494 m
DIE size = 1.49 x 1.69 mm; PAD size = 80 x 80 m Note: Because the substrate of the die is internally connected to VDD, the die has to be connected to VDD or left floating. Please make sure that VDD is the first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die. Pad Identification Power Supply Voltage Quartz Filter Output for Crystal 2 Quartz Filter Output for Crystal 1 Quartz Filter Input for Crystals AGC Capacitor Power Down/Frequency Selection Input 2 Receiver Output Demodulator Capacitor AGC On Control Power Down/Frequency Selection Input 1 Positive Receiver Input Negative Receiver Input Receiver Input 2 (for Antenna Capacitor 2) Power Supply Ground Name VDD QO2 QO1 QI AGC PDN2 OUT DEC AON PDN1 RFIP RFIM RFI2 VSS X-coordinate 174 m 174 m 174 m 174 m 174 m 174 m 175 m 1318 m 1318 m 1318 m 1318 m 1318 m 1318 m 1318 m Y-coordinate 1452 m 1247 m 1043 m 839 m 633 m 430 m 224 m 240 m 444 m 648 m 853 m 1057 m 1262 m 1466 m Note
1688 m
3 1 2 3 4 4
Notes: 1) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 A - at power down the output is pulled to VSS (pull down switch) 2) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 A which is switched off at power down 3) PDN1 = VDD and PDN2 = VDD means receiver off - Fast start-up is triggered when the receiver is after power down controlled to power up 4) Receiver inputs RFIP and RFIM have both 600 k biasing resistances against ground
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DA9081.006 1 August, 2005
FREQUENCY SELECTION
The frequency selection and power down control is accomplished via two digital control pins PDN1 and PDN2. The control logic is presented in table 1. Table 1 Frequency selection and power down control PDN1 PDN2 RFI2 Switch Selected Crystal Output High High Low Low High Low High Low Open Open Closed Closed QO1 QO2 QO2
Description Power down Frequency 1 Frequency 2, RFI2 capacitor connected in parallel with antenna Frequency 2, RFI2 capacitor connected in parallel with antenna If frequency 2 is selected then RFI2 switch is closed to connect CANT2 in parallel with ferrite antenna and tune it to frequency 2. Then only crystal output QO2 is active. Frequency 2 is lower frequency of the two selected frequencies. It is recommended to switch the device to power down for 50ms before switching to another frequency. This guarantees fast startup in switching to another frequency. The 50ms power down period is used to discharge AGC capacitor and to initialize fast startup conditions.
The internal antenna tuning capacitor switch (RFI2) and crystal filter output switches (QO1, QO2) are controlled according table 1. See switch in block diagram on page 1. If frequency 1 is selected the RFI2 switch is open and only crystal output QO1 is active. Antenna frequency is determined by antenna inductor LANT (see Typical Application on page 5), antenna capacitor CANT1 and parasitic capacitances related to antenna inputs RFI1, RFI2 and RFI3 (see Antenna Tuning Considerations below). Frequency 1 is the higher frequency of two selected frequencies.
ANTENNA TUNING CONSIDERATIONS
The ferrite bar antenna having inductance LANT and parasitic coil capacitance CCOIL is tuned to two reception frequencies f1 and f2 by parallel capacitors CANT1 and CANT2. The receiver input stage and internal antenna capacitor switch have capacitances (CRFI1, COFF2) which affect the resonance Frequency f1 (higher frequency): CTOT1=CCOIL+CANT1+CRFI1+COFF2=CCOIL+CANT1+6.5pF+37pF=CCOIL+CANT1+ 43.5pF, f 1 = Frequency f2 (lower frequency): CTOT2=CCOIL+CANT1+CANT2+CRFI1=CCOIL+CANT1+CANT2+ 6.5pF, f 2 = frequencies. COFF2 is switch capacitance when switch is open. When the switch is closed this capacitance is shorted by on resistance of the switch and is effectively eliminated. Following relationships can be written into two tuning frequencies.
1 2 L ANT C TOT 1
1 2 L ANT C TOT 2
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DA9081.006 1 August, 2005
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VDD-VSS VIN PMAX TOP TST Conditions Min -0.3 VSS-0.3 -40 -55 Max 6 VDD+0.3 100 +85 +150 Unit V V mW o C o C
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 1.4V, Temperature = 25 C
Parameter Operating Voltage Current Consumption
Symbol VDD IDD
Conditions VDD=1.4 V, Vin=0 Vrms VDD=1.4 V, Vin=20 mVrms VDD=3.6 V, Vin=0 Vrms VDD=3.6 V, Vin=20 mVrms
Min 1.10
Typ 64 37 67 40
Max 5
Unit V A
31 27 40
Stand-By Current Input Frequency Range Minimum Input Voltage Maximum Input Voltage Receiver Input Resistance Receiver Input Capacitance RFI2 Switch On Resistance RFI2 Switch Off Resistance RFI2 Switch Off Capacitance Input Levels |lIN|<0.5 A Output Current VOL<0.2 VDD;VOH >0.8 VDD Output Pulse
IDDoff fIN VIN min VIN max RRFI CRFI RON2 ROFF2 COFF2 VIL VIH |IOUT| T100ms T200ms T500ms T800ms
0.4 20 f=40kHz..77.5 kHz VDD=1.4 V 10 37 270 6.5 3.8
91 65 0.1 100 1
A kHz Vrms mVrms k pF M pF
0.2 VDD 0.8 VDD 5 1 Vrms VIN 20 mVrms 1 Vrms VIN 20 mVrms 1 Vrms VIN 20 mVrms 1 Vrms VIN 20 mVrms Fast Start-up, Vin=0.4 Vrms Fast Start-up, Vin=20 mVrms 50 150 400 700 500 800 1.3 3.5 50 140 230 600 900
V A ms ms ms ms s
Startup Time Output Delay Time
TStart TDelay
100
ms
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DA9081.006 1 August, 2005
TYPICAL APPLICATION
Note 1 X2 X1 Optional Control for AGC on/hold QI AON Demodulator & Comparator OUT Receiver Output
QO2 RFIP LANT Ferrite Antenna CANT1 CANT2 RFIM
QO1
AGC Amplifier
Power Supply/Biasing RFI2 VDD VBATTERY VSS PDN1 PDN2 AGC + DEC CAGC CDEC
Power Down / Fast Startup / Frequency Selection
Note 2
Figure 1
Application circuit of dual band receiver MAS9081
X2 40.003kHz X1 60.003kHz Optional Control for AGC on/hold QI AON Demodulator & Comparator OUT Receiver Output
QO2 RFIP LANT 4.40 mH Ferrite Antenna CANT1 1.5 nF CANT2 2.0 nF
QO1
AGC Amplifier RFIM
RFI2
Power Supply/Biasing VDD VSS PDN1 PDN2 AGC DEC + CAGC 10 F Power Down / Fast Startup / Frequency Selection CDEC 47 nF
1.4 V
Figure 2
Example circuit of dual band receiver MAS9081 for MSF/WWVB/JJY frequencies
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DA9081.006 1 August, 2005
TYPICAL APPLICATION (Continued)
Note 1: Crystals The crystals as well as ferrite antenna frequencies are chosen according to the time-signal system (Table 2). The crystal shunt capacitance C0 should be matched as well as possible with the internal shunt capacitance compensation capacitor CC of MAS9081. See Compensation Capacitance Options on table 3. Table 2 Time-Signal System Frequencies Time-Signal System Location DCF77 HGB MSF WWVB JJY BPC Germany Switzerland United Kingdom USA Japan China
Antenna Frequency 77.5 kHz 75 kHz 60 kHz 60 kHz 40 kHz and 60 kHz 68.5 kHz
Recommended Crystal Frequency 77.503 kHz 75.003 kHz 60.003 kHz 60.003 kHz 40.003 kHz and 60.003 kHz 68.505 kHz
Table 3 Compensation Capacitance Options Device CC Crystal Description MAS9081A1 MAS9081A3 MAS9081A4 MAS9081A5 0.75 pF 1.25 pF 1.5 pF 3.875 pF For low C0 crystal For high C0 crystal For high C0 crystal For any crystal (over compensated, requires external capacitors)
It should be noted that grounded crystal package has reduced shunt capacitance. This value is about 85% of floating crystal shunt capacitance. For example crystal with 1pF floating package shunt capacitance can have 0.85pF grounded package shunt capacitance. PCB traces of crystal and external compensation capacitance should be kept at minimum to minimize additional parasitic capacitance which can cause capacitance mismatching. Highest frequency crystal is connected to crystal output pin 1 (QO1). Lowest frequency crystal is connected to crystal output pin 2 (QO2). The other pin of both crystals is connected to common crystal input pin QI. Table 4 below presents some crystal manufacturers having suitable crystals for timesignal receiver application. Table 4. Crystal Manufacturers and Crystal Types in Alphaphetical Order for Timesignal Receiver Application Manufacturer Crystal Type Dimensions Web Link Citizen Epson KDS Daishinku Microcrystal Seiko Instruments CFV-206 C-2-Type C-4-Type DT-261 MX1V-L2N MX1V-T1K VTC-120 o 2.0 x 6.0 o 1.5 x 5.0 o 2.0 x 6.0 o 2.0 x 6.0 o 2.0 x 6.0 o 2.0 x 8.1 o 1.2 x 4.7 http://www.citizen.co.jp/tokuhan/quartz/ http://www.epsondevice.com/e/ http://www.kdsj.co.jp/english.html http://www.microcrystal.com/ http://speed.sii.co.jp/pub/compo/quartz/topE.jsp
Note 2: AGC Capacitor The AGC and DEC capacitors must have low leakage currents due to very small signal currents through the capacitors. The insulation resistance of these capacitors should be at minimum 100 M. Also probes with at least several 100 M impedance should be used for voltage probing of AGC and DEC pins. DEC capacitor can be low leakage chip capacitor.
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DA9081.006 1 August, 2005
MAS9081 SAMPLES IN SBDIL 20 PACKAGE
NC 1 VDD 2 QO2 3 QO1 4 NC 5 NC 6 QI 7 AGC 8 PDN2 9 OUT 10
9081Az YYWW XXXXX.X
20 VSS 19 RFI2 18 RFIM 17 RFIP 16 NC 15 NC 14 PDN 1 13 AON 12 DEC 11 NC
Top Marking Definitions: YYWW = Year Week XXXXX.X = Lot Number z = Sample Version Number
PIN DESCRIPTION
Pin Name NC VDD QO2 QO1 NC NC QI AGC PDN2 OUT NC DEC AON PDN1 NC NC RFIP RFIM RFI2 VSS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Type P AO AO Function Positive Power Supply Quartz Filter Output for Crystal 2 Quartz Filter Output for Crystal 1 1 1 AI AO DI DO AO DI DI Quartz Filter Input for Crystals AGC Capacitor Power Down/Frequency Selection Input 2 Receiver Output Demodulator Capacitor AGC On Control Power Down/Frequency Selection Input 1 Note
2
3
AI AI AI G
Positive Receiver Input Negative Receiver Input Receiver Input 2 (for Antenna Capacitor 2) Power Supply Ground
4 4
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Notes: 1) Pins 5 and 6 between QO and QI must be connected to VSS to eliminate DIL package leadframe parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also recommended to be connected to VSS to minimize noise coupling. 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 A - at power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 A which is switched off at power down 4) Receiver inputs RFIP and RFIM have both 600 k biasing MOSFET-transistors towards ground
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DA9081.006 1 August, 2005
PIN CONFIGURATION & TOP MARKING FOR PLASTIC TSSOP-16 PACKAGE
VDD QO2 QO1 NC QI AGC PDN2 OUT VSS RFI2 RFIM RFIP NC PDN1 AON DEC
9081Az
YYWW
Top Marking Definitions: z = Version Number YYWW = Year Week
PIN DESCRIPTION
Pin Name VDD QO2 QO1 NC QI AGC PDN2 OUT DEC AON PDN1 NC RFIP RFIM RFI2 VSS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type P AO AO AI AO DI DO AO DI DI AI AI AI G Function Positive Power Supply Quartz Filter Output for Crystal 2 Quartz Filter Output for Crystal 1 1 Quartz Filter Input for Crystal and External Compensation Capacitor AGC Capacitor Power Down/Frequency Selection Input 2 Receiver Output Demodulator Capacitor AGC On Control Power Down/Frequency Selection Input 1 Positive Receiver Input Negative Receiver Input Receiver Input 2 (for Antenna Capacitor 2) Power Supply Ground Note
2 3
4 4
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Notes: 1) Pin 4 between quartz crystal filter pins must be connected to VSS to eliminate package leadframe parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also recommended to be connected to VSS to minimize noise coupling. 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 A - at power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up (to AGC on) with current < 1 A which is switched off at power down 4) Differential input versions A1..A5 have 600 k biasing MOSFET-transistors towards ground from both receiver inputs RFIP and RFIM. Asymmetric input versions AB..AF have input pin RFIM unconnected.
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DA9081.006 1 August, 2005
PACKAGE (TSSOP-16) OUTLINES
C
E D Seating Plane B A O Pin 1 Detail A F G H
B B
L I I1 K P Section B-B J1 J M N
Detail A
Dimension A B C D E F G H I I1 J J1 K L M (The length of a terminal for soldering to a substrate) N O P
Min 6.40 BSC 4.30 5.00 BSC 0.05 0.19 0.65 BSC 0.18 0.09 0.09 0.19 0.19 0 0.24 0.50
Max 4.50 0.15 1.10 0.30 0.28 0.20 0.16 0.30 0.25 8 0.26 0.75
Unit mm mm mm mm mm mm mm mm mm mm mm mm mm mm
1.00 REF 12 12
mm
Dimensions do not include mold flash, protrusions, or gate burrs. All dimensions are in accordance with JEDEC standard MO-153.
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DA9081.006 1 August, 2005
SOLDERING INFORMATION
N For Pb-Free, RoHS Compliant TSSOP-16 Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile Seating Plane Co-planarity Lead Finish According to RSH test IEC 68-2-58/20 260C 3 Thermal profile parameters stated in IPC/JEDEC J-STD-020 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 m, material Matte Tin
EMBOSSED TAPE SPECIFICATIONS
Tape Feed Direction P0 D0 P2
A E1 F1 W
D1 A P A0 Tape Feed Direction T Section A - A B0 S1 K0
Dimension A0 B0 D0 D1 E1 F1 K0 P P0 P2 S1 T W Min 6.50 5.20 1.50 +0.10 / -0.00 1.50 1.65 7.20 1.20 11.90 4.0 1.95 0.6 0.25 11.70 2.05 0.35 12.30 1.85 7.30 1.40 12.10
Pin 1 Designator
Max 6.70 5.40 Unit mm mm mm mm mm mm mm mm mm mm mm mm mm
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DA9081.006 1 August, 2005
REEL SPECIFICATIONS
W2
A
D B
Tape Slot for Tape Start
C
N
W1
2000 Components on Each Reel Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative Carrier Tape
Cover Tape End
Start
Trailer
Dimension A B C D N W1 (measured at hub) W2 (measured at hub) Trailer Leader Min
Components
Max 330 1.5 12.80 20.2 50 12.4 13.50
Leader
Unit mm mm mm mm mm mm mm mm mm
14.4 18.4
160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape 1500
Weight
g
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DA9081.006 1 August, 2005
ORDERING INFORMATION
Product Code MAS9081A1TC00 MAS9081A3TC00 MAS9081A4TC00 MAS9081A5TC00 MAS9081A1UC06 Product Dual Band AM-Receiver IC with Differential Input Dual Band AM-Receiver IC with Differential Input Dual Band AM-Receiver IC with Differential Input Dual Band AM-Receiver IC with Differential Input Dual Band AM-Receiver IC with Differential Input Description EWS-tested wafer, Thickness 400 m. EWS-tested wafer, Thickness 400 m. EWS-tested wafer, Thickness 400 m. EWS-tested wafer, Thickness 400 m. TSSOP-16, Pb-free, RoHS compliant, Tape & Reel Capacitance Option CC = 0.75 pF CC = 1.25 pF CC = 1.5 pF CC = 3.875 pF CC = 0.75 pF
Contact Micro Analog Systems Oy for other wafer thickness options.
LOCAL DISTRIBUTOR
MICRO ANALOG SYSTEMS OY CONTACTS
Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com
NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
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